In a known way, phase change non-volatile memories, for example, ePCMs (embedded Phase change Memories), represent a new generation of integrated memories, in which, to store information, the characteristics of materials having the property of switching between phases having different electrical characteristics are exploited. These materials may switch between an amorphous, disorderly, phase and a crystalline or polycrystalline, orderly, phase and resistivities of considerably different value, and consequently a different value of a datum stored, are associated with the two phases. For example, the elements of the VI group of the periodic table, such as tellurium (Te), selenium (Se), or antimony (Sb), referred to as chalcogenides or chalcogenic materials, can be advantageously used for manufacturing phase change memory cells. In particular, an alloy made up of germanium (Ge), antimony (Sb), and tellurium (Te), known as GST (having the chemical composition Ge2Sb2Te5) is currently widely used in such memory cells. The phase changes may be obtained by locally increasing the temperature of the cells of chalcogenic material through resistive electrodes (generally known as heaters) set in contact with respective regions of chalcogenic material.
Access devices (for example, metal oxide semiconductor field effect transistors ((MOSFETs)), are connected to the heaters and selectively enable passage of a programming electric current through a respective heater. This electric current, by the Joule effect, generates the temperatures for the phase change. In particular, when the chalcogenic material is in the amorphous state, at high resistivity (the so-called RESET state), a current/voltage pulse (or a suitable number of current/voltage pulses) of duration and amplitude is applied to enable the chalcogenic material to cool slowly. Subjected to this treatment, the chalcogenic material changes its state and switches from the high-resistivity state to a low-resistivity state (the so-called SET state), and vice versa, when the chalcogenic material is in the SET state. More particularly, when the chalcogenic material is in the SET state, a current/voltage pulse having suitable duration and high amplitude is applied to cause the chalcogenic material to return into the high-resistivity amorphous state.
During reading, the state of the chalcogenic material is detected by applying a voltage sufficiently low as not to cause a sensible heating thereof, and then reading the value of the current that flows in the memory cell. Given that the current is proportional to the conductivity of the chalcogenic material, it may be possible to determine in which state the material is, and consequently, determine the datum stored in the memory cell.
In general, PCMs may have several advantages, for example, high scalability and reading speed combined with a reduced current consumption and a high efficiency. In a known way, and as shown schematically in FIG. 1 (limited to the parts for the description of the present embodiments), a non-volatile PCM device, designated by 1, generally comprises a memory array 2 made up of a plurality of memory cells 3, arranged in rows (wordlines, WL) and columns (bitlines, BL).
Each memory cell 3 includes a storage element 3a and an access element 3b, which are connected in series between a respective bitline BL and a terminal at reference potential (for example, ground, Gnd). In particular, a wordline WL is defined by the set of the control terminals of the access elements 3b aligned along one and the same row.
The storage element 3a includes a phase change material (for example, a chalcogenide, such as GST), and is, consequently, able to store data in the form of resistance levels associated with the different phases assumed by the same material (for this reason, in the attached figures it will at times be modelled as a resistor with variable resistance). The access element 3b, as in the embodiment illustrated, is an N-channel complementary metal oxide semiconductor (CMOS) transistor having its gate terminal connected to a respective wordline WL, its drain terminal connected to the storage element 3a, and its source terminal connected to the reference potential terminal. The access element 3b is controlled and biased to enable, when selected, the passage of a reading/programming driving current through the storage element 3a, having an appropriate value during respective reading/programming operations.
A column decoder 4 and a row decoder 5 enable selection of the memory cells 3, based upon the address signals received at input (generated in a known way and designated as a whole by AS) and relatively complex decoding schemes, and, in particular, selection of the corresponding wordlines WL and bitlines BL each time addressed, enabling biasing thereof at suitable voltage and current values. In particular, it is known that during programming operations, both when programming of the SET state and when programming of the RESET state of the chalcogenide material of the memory cells 3, supplying high-value current pulses to the storage elements 3a is desired for activation of the mechanisms of change of state. For example, programming of the SET state may be obtained via a rectangular current pulse having an amplitude between 200 μA and 300 μA, whereas programming of the RESET state may be obtained via a rectangular current pulse having an amplitude comprised between 500 μA and 700 μA.
The voltage on the selected bitline BL may be expressed via the following relation:VBL=RGST·I+VDS where RGST is the resistance value of the storage element 3a, I is the current circulating through it, and VDS is the voltage drop between the drain and source terminals of the access element 3b. 
Considering a value of the resistance RGST of approximately 2.5 kΩ and a voltage drop VDS between 1 V and 1.5 V, the voltage on the bitline VBL may reach values in the region of 3 V. It follows that the voltage supplied to the column decoder 4 be higher than this value, for example, equal to 3.6 V, to enable the passage of the desired current during the programming step.
The column decoder 4 is moreover advantageously configured for providing, internally, two distinct paths towards the bitlines BL of the memory array 2 each time selected. The first path is a reading path to selectively create a conductive path between the selected bitline BL and a sense-amplifier stage 7 configured to compare the current circulating in the addressed memory cell 3 with a reference current to determine the datum stored. The second path is a programming path to selectively create a conductive path between the selected bitline BL and a driving stage 8 configured to supply the high currents for the programming operations of the SET and RESET states.
For this purpose, as will on the other hand be described in detail in what follows, the column decoder 4 comprises, for each reading and programming path, suitable selection elements, in particular, controlled transistors, connected in a cascaded fashion and configured for implementing a hierarchical address decoding for selection of the memory cells 3. In particular, as shown schematically in FIG. 2, the memory array 2 is generally arranged in a plurality of sectors, each of which comprises a plurality of memory cells 3. Each sector has a plurality of respective local bitlines designated once again by BL (distinct from those of the other sectors), and which are physically connected to the memory cells 3 of the memory array 2 present in the same sector. In addition, for each group of local bitlines BL, for example, four in number, two main bitlines MBL are provided, one for reading, designated by MBLr, and one for programming, designated by MBLp, when selected, at a higher hierarchical level, to enable subsequent selection at a lower hierarchical level of one or more of the respective local bitlines BL and of the corresponding memory cells 3. The main bitlines MBL traverse a number of sectors and may be selected in groups at a hierarchical decoding level still higher than the one associated with selection of the main bitlines MBL.
The column decoder 4 hence comprises, for each sector, at least one respective first-level decoding circuit for the reading operations and for the (SET and RESET) programming operations, coupled to, and operable for selecting, the respective local bitlines BL. The column decoder 4 also includes, for each group of sectors, a respective second-level decoding circuit, once again for the reading operations and for the programming operations, coupled to, and operable for selecting, the respective main bitlines MBL (as previously highlighted, also a decoding circuit at a still higher level, for selection in groups of the main bitlines MBL, possibly being provided).
In a known way, the decoding circuits for the reading operations are provided with N-channel CMOS transistors, whereas the decoding circuits for the programming operations are provided with P-channel CMOS transistors. The various CMOS transistors are, in any case given the high voltages that may occur in the various operating conditions, high-voltage transistors, i.e., transistors having oxides of large thicknesses.
In this regard, it is known, for example, that using 90-nm CMOS technology it is possible to provide low-voltage transistors (for example, ones using voltages ranging between 1.08 V and 1.32 V, equal to a logic voltage Vdd of the memory device 1, and able to withstand, for a short period of time, operating voltages of slightly higher values, for example equal to 1.8 V) having a smaller thickness of the gate oxide and a smaller occupation of area. Using 90-nm CMOS technology, it also possible to provide high-voltage transistors, i.e., ones designed to withstand higher operating voltages, with a maximum value, for example, between 1.55 V and 5.5 V, i.e., of a value higher or much higher than the logic voltage Vdd, and having a large thickness of the gate oxide and high occupation of area. High-voltage CMOS transistors are moreover used also for providing the biasing stages for biasing the wordlines WL (i.e., for biasing the control terminals of the access elements 3b of the memory cells 3), given the high voltages on the same control terminals for enabling the effective transfer of the programming currents and the presence of the desired voltages on the bitlines BL.
Known decoding architectures for PCM devices hence suffer from some limitations that do not enable full exploitation of their advantages. In particular, the use of a high number of high-voltage CMOS transistors for row and column decoding evidently entails a high occupation of area in the integrated implementation, whilst the possible use of dedicated masks and implants of dopants would entail high manufacturing costs. Moreover, the use of boosted voltages (to obtain the required voltage values) both in programming and in reading entails a high dynamic energy consumption.